The semiconductor industry is constantly striving to improve the Integrated Circuits (IC) by: 1) reducing their operating delay, 2) adding more functionality and complexity, 3) adding more versatility, and 4) reducing the size. The complete and flawless global planarization of the thin film materials that form the wiring of the present day integrated circuit (IC) is one of the most prominent challenges in front of the semiconductor industry today.
With the incorporation of polymeric low dielectric constant materials (low k) in the IC wiring to increase the circuit speed, the demand for effective planarization has increased dramatically. Chemical Mechanical Polishing (CMP) process is universally used to planarize the constituent thin films of the IC interconnect wiring scheme. Compared to the other materials in the IC (e.g. Silicon, Tungsten, Silica, etc.), polymeric low k materials are much softer as compared to the abrasive particles used in the chemical active solution used (CMP Slurry) during the polishing process.
Hence, controlling polymeric ILD polishing to meet the stringent demands of the semiconductor industry and producing IC wiring without: 1) micro/nano scratching, 2) over polish, pattern damage, trough formation, etc, 3) material delamination, etc. is of paramount importance to make more sophisticated and cost effective chips of tomorrow.